Electronic devices generally include a host circuit board populated with components such as integrated circuits (ICs), which are provided in a variety of surface-mount or through-hole packages. ICs can be soldered directly onto the host printed circuit board (PCB) or mounted via a socket. It is generally important that each IC be oriented correctly on the host circuit board, so as to avoid damage at power-on.
This is an ongoing issue since most ICs have a rotationally symmetric footprint, that is, their electrical contacts (e.g. pins or pads) can physically align with corresponding connection locations (e.g. vias or pads) of the host circuit board for more than one rotational position of the IC. For example, in the case of a square IC with contacts on all four edges or in a grid pattern, the IC can be rotated in 90 degree increments and still align with its host connection location. In the case of a rectangular IC, the increments can be 180 degree increments. Although the footprint is physically rotationally symmetric, the IC pinout is not typically symmetric, and hence damage can occur if the IC is incorrectly oriented.
Correct IC orientation is typically addressed either by marking the host circuit board and IC so that the installer knows and follows the correct orientation, or by physically shaping the integrated circuit and host location to destroy symmetry, so that incorrect orientation is physically difficult or impossible to achieve. A typical example of such an arrangement includes “cutting” one corner off of a rectangular IC and “filling” the corresponding corner of its host socket, to inhibit mis-orientation.
Particularly for smaller ICs, marking can be difficult to see. Furthermore, physical symmetry-destroying features of small ICs may be too small to properly guard against mis-orientation since their size may be inadequate to resist a relatively small amount of insertion force.
Therefore there is a need for a means of guarding against mis-orientation of ICs that is not subject to one or more limitations of the prior art.
This background information is provided for the purpose of making known information believed by the applicant to be of possible relevance to the present technology. No admission is necessarily intended, nor should be construed, that any of the preceding information constitutes prior art against the present technology.